A New Arbitration Circuit for Synchronous Multiple Bus Multiprocessor Systems

In a shared memory multiprocessor system, two or more processors may simultaneously request the use of a shared resource. Therefore, an arbitration circuit is essential to resolve the contention among the competing processors and allocate the resource to the appropriate requesting processor (according to an arbitration protocol). A number of arbiter desians for multiDrocessor systems have been reported in the literature [i-91. But the designs presented in [l-71 are suitable for single bus multiprocessor systems. An one-step programmable arbiter is proposed by K. Hojberg [l], in which only one state transition is required from a free to an allocated resource with arbiter structure and status programmed into state machine memory. A multirequest and uniserver arbiter has been presented in [3] which adopted an asynchronous, centralized scheme. For a multiprocessor system with large number of processors and memory modules, a centralized bus arbiter may become a serious bottleneck since all bus requests must be handled by one arbiter which will seriously affect the performance and reliability of the system. The most widely accepted arbiter for single bus asynchronous multiprocessor systems has been invented by D.M. Taub [5] and is implemented in IEEE 896 futurebus. For a detailed analysis of arbitration protocols and their implementation for single bus multiprocessor systems, the reader is referred to reference [7]. References [8-91 addressed the arbitration mechanism for multiple bus multiprocessor systems. A synchronous M-user B-server arbiter is proposed for a multiple bus system by T. Lang and M. Valero 191. In this architecture, a lookahead technique is used to reduce the delay of arbitration process. The authors presented three different designs, viz., iterative, 1 -level lookahead, and 2-level lookahead for this arbiter. The iterative design Syed Masud Mahmud and Md. Showkat-UCAlam